1. Field of the Invention
The present disclosure generally relates to the fabrication of semiconductor devices, and, more particularly, to a method for making single fin cuts using selective ion implants.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area. In integrated circuits fabricated using metal-oxide-semiconductor (MOS) technology, field effect transistors (FETs) (both NMOS and PMOS transistors) are provided that are typically operated in a switching mode. That is, these transistor devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). FETs may take a variety of forms and configurations. For example, among other configurations, FETs may be either so-called planar FET devices or three-dimensional (3D) devices, such as finFET devices.
A field effect transistor (FET), irrespective of whether an NMOS transistor or a PMOS transistor is considered, and irrespective of whether it is a planar or 3D finFET device, typically comprises doped source/drain regions that are formed in a semiconductor substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. The gate insulation layer and the gate electrode may sometimes be referred to as the gate structure for the device. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region. In a planar FET device, the gate structure is formed above a substantially planar upper surface of the substrate. The gate structures for such planar FET devices may be manufactured using so-called “gate-first” or “replacement gate” (gate-last) manufacturing techniques.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation distance between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, a so-called finFET device has a three-dimensional (3D) structure. FIG. 1A is a perspective view of an illustrative prior art finFET semiconductor device 100 that is formed above a semiconductor substrate 105. In this example, the finFET device 100 includes five illustrative fins 110, 115, a gate structure 120, sidewall spacers 125 and a gate cap 130. The finFET device 100 implements two different transistor devices with a shared gate structure. The gate structure 120 is typically comprised of a layer of insulating material (not separately shown), e.g., a layer of high-k insulating material or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode for the device 100. The fins 110, 115 have a three-dimensional configuration. The portions of the fins 110, 115 covered by the gate structure 120 define the channel regions of the finFET device 100. An isolation structure 135 is formed between the fins 110, 115. The fins 110 are associated with a transistor device of a first type (e.g., N-type), and the fins 115 are associated with a transistor device of a complementary type (e.g., P-type). The gate structure 120 is shared by the N-type and P-type transistors, a common configuration for memory devices, such as static random access memory (SRAM) cells.
Typically, fins are formed in a regular array. To provide separation between the first group of fins 110 and the second group of fins 115 to facilitate separate processing and to electrically isolate the two different devices, one or more of the fins in the array are removed prior to forming the gate structure. Selected fins may be removed after they are formed (fins-cut-last), or the hard mask used to etch the fins may be modified to remove a fin mask element prior to etching the fins (fins-cut-first).
As illustrated in FIG. 1B, one technique for removing a selected fin feature 135 (actual fin or hard mask fin element) is to form a dielectric layer 140 above the fins, pattern a photoresist layer 145 to define an opening 150 above the selected fin 135, and perform an etch process to remove the dielectric material 140 to expose the fin 135. The fin 135 may be removed by a subsequent etch process. When exposing the fin 135, the etch process may also expose or damage adjacent fins due to alignment errors or to imperfect anisotropic etch processes (i.e., where an isotropic component is present), as indicated by the circled exposed edge 152. These unintentionally exposed fins may be further damaged during the etch process to remove the fin 135. This damage can lead to reduced performance or defects.
FIGS. 1C-1E illustrate another technique for removing a selected fin. As illustrated in FIG. 1C, a fin mask layer includes a plurality of mandrel elements 150 with sidewall spacers 155A, 155B formed thereon. Additional hard mask layers (e.g., silicon nitride and silicon dioxide) may be formed beneath the mandrel elements 150 and spacers 155A, 155B, but these layers are omitted for ease of illustration. The mandrel elements 150 are removed prior to etching the fins, thus leaving the spacers 155A, 155B in place as the etch mask that is positioned above the underlying layer(s) to be patterned (e.g., the hard mask layers, followed by the substrate material), a technique referred to as sidewall spacer image transfer. A blanket angled ion implantation process is performed to change the etch characteristics of the spacers 155B on the sides of the mandrel elements exposed to the implantation.
In FIG. 1D, a photoresist layer 160 is formed above the mandrel elements 150 and the spacers 155A, 155B and patterned to expose a selected spacer 155C. An etch process is performed to remove the selected spacer 155C. Due to the relative differences in etch characteristics between the spacers 155A and the selected spacer 155C (as a result of the aforementioned ion implantation process), the selected spacer 155C can be selectively removed even though some of the spacers 155A are also exposed to the etching process.
As illustrated in FIG. 1E, after the photoresist layer 160 and mandrel elements are removed, the remaining spacers 155B, 155A are used as a patterned etch mask to etch the fins and/or one or more layers of insulating material positioned between the etch mask and the substrate 105. However, because the etch mask includes both spacers 155B, 155A, with differing etch characteristics, the subsequent etch process(es) to form the fins are less predictable and may exhibit reliability issues.
The present disclosure is directed to various methods and resulting devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.